Abstract
<title>Abstract</title> <p>In today’s digital world, the information and transactions are protected and authenticated using cryptographic hash functions. SHA-256 is a reliable one-way hash function with high resistance against collision, security and speed. Previous research works have found that the hardware implementation of SHA-256 algorithm is more efficient and scalable in comparison to the software counterpart. With advanced embedded and IoT applications, the low power efficient design of SHA-256 accelerator for edge devices (with limited power) is required. In this paper, we propose an SHA-2 hardware accelerator architecture for resource constrained edge devices as well as IoT nodes. To achieve high performance, we introduced 2X loop unrolling to reduce computation latency and streamlined control logic to avoid redundant operations. The Proposed SHA-256 architecture is resource optimized to minimize hardware utilization like number of LUTs and FFs. Further, low power technique such as clock gating is applied to reduce the dynamic power consumption. The proposed SHA-2 design is verified and tested using Xilinx Vivado 2025.1 platform and implemented on Field Programmable Gate Array (FPGA) board (Nexys A7). The obtained results shows that the proposed SHA-2 accelerator architecture achieves a throughput of 1.47 (Mhps) and a power of 0.11 (W). The evaluation results for energy efficiency indicates that the proposed design of SHA-2 accelerator achieves upto 13.37 (Mhps/W) and hence suitable for low power edge devices utilized in embedded IoT applications.</p>