A Fully Streaming Low-Latency FPGA Architecture for Range-Doppler SAR Processing Using Radix-2 SDF FFT

<title>Abstract</title> <p>Conventional FPGA implementations of the Range-Doppler Algorithm (RDA) execute range and azimuth compression sequentially, requiring the complete range-compressed data frame to be stored in a centralized two-dimensional buffer before azimuth processing can begin. This frame-oriented organization introduces significant processing latency and reduces temporal efficiency by forcing range and azimuth processing to execute sequentially. This paper presents a fully streaming FPGA architecture that replaces the centralized frame buffer with distributed stage-wise delay memories embedded within radix-2 Single-Path Delay Feedback (SDF) FFT/IFFT pipelines. By exploiting complementary DIF/DIT processing, the proposed architecture enables azimuth processing to start immediately after the first Ns range-compressed samples become available, allowing range and azimuth compression to operate concurrently without explicit frame-level buffering. Unlike conventional approaches, the proposed architecture reorganizes rather than reduces the required memory, transforming it into an integral part of the streaming pipeline. FPGA implementation results demonstrate deterministic real-time operation with a sustained throughput of one complex sample per clock cycle after pipeline filling. For Nr = 512 and Ns = 1024, the first-output latency is reduced from 525,824 to 2,048 clock cycles, while the total frame processing time decreases from 1,050,112 to 526,336 clock cycles. These results demonstrate that substantial performance improvement can be achieved through streaming architectural scheduling without modifying the underlying RDA or increasing its computational complexity.</p>