Abstract
<title>Abstract</title> <p>Charge-trapping optoelectronic synapses based on two-dimensional semiconductors are promising building blocks for in-sensor neuromorphic vision, yet their evaluation still relies on empirical double-exponential fits and lookup-table network simulations that cannot capture the underlying trap dynamics. Here, a physics-based compact model of MoS 2 phototransistor synapses is presented, which couples a multi-level trap-kinetics ladder, solved exactly in closed form for arbitrary optical pulse trains, to a smooth field-effect-transistor transducer. Calibrated against digitized measurements from two independently published devices–a monolayer MoS 2 /SiO 2 transistor and a CdSe-sensitized MoS 2 heterostructure–a single trap-ladder framework (with the number of levels selected by information criteria) reproduces paired-pulse facilitation (PPF) and multi-decade retention, and independently recovers the empirically reported relaxation constants. The model yields two analytical insights: apparent PPF time constants are emergent quantities limited by the optical pulse width rather than fundamental trap parameters, and linear charge accumulation bounds the PPF index at 200%, so that larger measured values necessarily encode transducer superlinearity, supplied in saturation by the square law and, below threshold, by the exponential regime. Exercising the calibrated model in a photo-programmed synaptic array reveals a design–technology co-optimization knob: reducing the programming irradiance reshapes the conductance ladder through the per-pulse trap filling, lowering training energy 6.7-fold at equal-or slightly-better recognition accuracy (92.6% to 93.4%, five-seed means). Finally, because every synapse carries explicit trap occupancies, the framework enables retention-aware analysis inaccessible to lookup-table approaches, quantifying inference-time weight decay, forgetting during slow training, and an optical-refresh design space sustaining a 94% accuracy floor at sub-microwatt standby power for the demonstrated 640-synapse array.</p>