Abstract
<title>Abstract</title> <p>The growing complexity of modern system-on-chip (SoC) architectures has intensified the threat of Hardware Trojans (HTs), which can maliciously alter functionality, leak sensitive data, or enable remote activation post-fabrication. While graph neural network (GNN), based detection frameworks have demonstrated strong performance on Register Transfer Level (RTL) designs, they are consistently evaluated under a single synthesis configuration, ignoring the profound structural variability that technology-node scaling introduces at the gate level. In the present work, a technology-node-aware HT detection framework, i.e. SubNM is proposed that systematically synthesizes the same 21 Trust-Hub RTL benchmark designs across four open-source standard cell libraries, (i) OSU180 (180 nm), (ii) TSMC90 (90 nm), (iii) NanGate45 (45 nm), and (iv) SAED28 (28 nm) using the Yosys open-source synthesis suite, thereby generating an 84-design multi-node corpus. Each synthesized netlist is hierarchically partitioned into semantically coherent graphs, which are processed by a GNN employing joint structural and technology-aware node embeddings augmented with a library one-hot encoding and normalized gate area. Cross-node evaluation protocol is introduced to measure generalization by training all the libraries and testing on single library file. Experiments demonstrate that individual libraries show average (min) TPR of 93.63%, 89.51%,85.12 and 78.68% for OSU180, TSMC90, NanGate45 and SAED28. However, after utilization of SubNM, the performance improves to 99.46%, 99.12%, 98.98% and 98.84 for OSU180, TSMC90, NanGate45 and SAED28. These results establish SubNM as a scalable, library-agnostic solution for pre-silicon hardware security assurance across the full contemporary technology spectrum.</p>